The present invention relates to a bipolar transistor (semiconductor device), and, more particularly, to a technique which is applicable effectively to a bipolar transistor having mesa-type semiconductor layers.
Studies are under way on bipolar transistors having a collector layer, a base layer and an emitter layer formed in this order in a transistor region on a semiconductor substrate, with remaining areas being etched off. These bipolar transistors, which have a collector, base and emitter layers of a trapezoidal cross section (shape of a “mesa”), are called mesa-type bipolar transistors.
Also studies are under way on bipolar transistors formed of a compound semiconductor of the III-V groups, such as gallium-arsenic (GaAs). Such a compound semiconductor is characterized by having a higher mobility as compared with Si (silicon) and by enabling the formation of semi-insulating crystal and mixed crystal to create hetero junctions.
For example, a hetero-junction bipolar transistor (HBT: Hetero-junction Bipolar Transistor) based on the use of gallium-arsenic is a bipolar transistor which is formed of GaAs for the base layer and which has a different semiconductor, such as InGaP (indium-gallium-phosphor), for the emitter layer. Using the hetero junction (different junction) to make the emitter forbidden band width of base-emitter junction larger than that of the base can improve the transistor characteristics, such as providing a larger current gain.
Patent document 1 discloses a hetero-junction bipolar transistor having a reduced base-emitter capacitance. The base electrode (1) and emitter electrode (2) of this transistor have rectangular patterns, and they are formed over a rectangular base layer (5).
[Patent document 1]
Japanese Patent Application Laid-Open No.2001-230261 (FIG. 1 and FIG. 2)